A 12-Bit 125MSps Binary-Scaled Redundant SAR ADC with Partial Split Capacitor DAC
Author:
Affiliation:
1. School of Electronics and Information Enaineering, Anhui University,Hefei,China,230601
2. East China Research Institute of Electronic Engineering,Hefei,China,230601
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10221938/10221896/10222537.pdf?arnumber=10222537
Reference9 articles.
1. A 12-Bit 100MS/s Subrange SAR ADC with a Foreground Offset Tracking Calibration Scheme;chung;IEEE Transactions on Circuits and Systems II-Exporess Briefs,2019
2. 60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration
3. Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC
4. A 1.2V 10b 20M Sample/s non-binary successive approximation ADC in 0.13?m CMOS;kuttner;IEEE ISSCC Dig Tech Papers,2002
5. A 0.0067-mm2 12-bit 20-MS/s SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS
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