Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems

Author:

Choi Jongsok,Nam Kevin,Canis Andrew,Anderson Jason,Brown Stephen,Czajkowski Tomasz

Publisher

IEEE

Cited by 28 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. BRAMAC: Compute-in-BRAM Architectures for Multiply-Accumulate on FPGAs;2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM);2023-05

2. Multipurpose Cacheing to Accelerate OpenMP Target Regions on FPGAs;OpenMP: Advanced Task-Based, Device and Compiler Programming;2023

3. Temporal Vectorization;Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design;2022-10-30

4. Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs;IEEE Access;2022

5. Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects;ACM Transactions on Reconfigurable Technology and Systems;2021-12-31

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