Design and Evaluation of On-chip DCT accelerators based on Novel Approximate Reverse Carry Propagate Adders

Author:

Singh Shalini1,Pothula Pavan Kumar1,Rao Madhav1

Affiliation:

1. IIIT Bangalore,VLSI Design Lab,Bangalore,India,560100

Publisher

IEEE

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Integrated MAC-based Systolic Arrays: Design and Performance Evaluation;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12

2. Efficient Radix-4 Approximated Modified Booth Multiplier for Signal Processing and Computer Vision: A Probabilistic Design Approach;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

3. PSO Optimized Design of Error Balanced Weight Stationary Systolic Array Architecture for CNN;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

4. OEDASA: Optimization Enabled Error-Diluted Approximate Systolic Array Design for an Image Processing Application;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

5. ApproxCNN: Evaluation Of CNN With Approximated Layers Using In-Exact Multipliers;2023 IEEE 41st International Conference on Computer Design (ICCD);2023-11-06

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