Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks-Reference-Cited by-同舟云学术

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Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks

Published:2020-07 Issue: Volume: Page:
ISSN:
Container-title:2020 57th ACM/IEEE Design Automation Conference (DAC)
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Author:

Zheng Qilin,Wang Zongwei,Feng Zishun,Yan Bonan,Cai Yimao,Huang Ru,Chen Yiran,Yang Chia-Lin,Li Hai Helen

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9211868/9218488/09218590.pdf?arnumber=9218590

Cited by 29 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. IMI: In-memory Multi-job Inference Acceleration for Large Language Models;Proceedings of the 53rd International Conference on Parallel Processing;2024-08-12

2. A Comprehensive Review of Processing-in-Memory Architectures for Deep Neural Networks;Computers;2024-07-16

3. Hybrid Digital/Analog Memristor-based Computing Architecture for Sparse Deep Learning Acceleration;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

4. Temperature-Dependent Accuracy Analysis and Resistance Temperature Correction in RRAM-Based In-Memory Computing;IEEE Transactions on Electron Devices;2024-01

5. Mathematical Framework for Optimizing Crossbar Allocation for ReRAM-based CNN Accelerators;ACM Transactions on Design Automation of Electronic Systems;2023-12-18

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