Efficiently Exploiting Low Activity Factors to Accelerate RTL Simulation

Author:

Beamer Scott,Donofrio David

Publisher

IEEE

Cited by 17 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Accelerating Loop-Oriented RTL Simulation With Code Instrumentation;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-12

2. IT-DSE: Invariance Risk Minimized Transfer Microarchitecture Design Space Exploration;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

3. The Essence of Verilog: A Tractable and Tested Operational Semantics for Verilog;Proceedings of the ACM on Programming Languages;2023-10-16

4. ERAS: A Flexible and Scalable Framework for Seamless Integration of RTL Models with Structural Simulation Toolkit;2023 IEEE International Symposium on Workload Characterization (IISWC);2023-10-01

5. Functional Verification for Agile Processor Development: A Case for Workflow Integration;Journal of Computer Science and Technology;2023-07

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