Author:
Beamer Scott,Donofrio David
Cited by
21 articles.
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1. CPGPUSim: A Multi-dimensional Parallel Acceleration Framework for RTL Simulation;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10
2. Accelerating Loop-Oriented RTL Simulation With Code Instrumentation;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-12
3. IT-DSE: Invariance Risk Minimized Transfer Microarchitecture Design Space Exploration;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28
4. Khronos: Fusing Memory Access for Improved Hardware RTL Simulation;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28
5. Accelerating RTL Simulation with Hardware-Software Co-Design;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28