Performance Optimization in Recessed Modified Junctionless FET
Author:
Affiliation:
1. Government College of Engineering,Tirunelveli,Tamil Nadu,India
2. Kalasalingam Academy of Research and Education,Virudhunagar,Tamilnadu,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9776594/9776641/09777109.pdf?arnumber=9777109
Reference18 articles.
1. Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors
2. Performance Analysis of Gate Electrode Work Function Variations in Double-gate Junctionless FET
3. Effect of Channel Width Variation on Electrical Characteristics of Double Lateral Gate Junctionless Transistors; A Numerical Study
4. Effect of Band-to-Band Tunneling on Junctionless Transistors
5. Junctionless transistors
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