Analysis of an Efficient Linear Congruential Generator Architecture for Digital Applications
Author:
Affiliation:
1. Sathyabama Institute of Science and Technology,Department of Electronics and Communication,Chennai,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10179605/10179606/10179609.pdf?arnumber=10179609
Reference20 articles.
1. High speed binary addition
2. Efficient hardware implementation of a new pseudo-random bit sequence generator
3. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
4. A General Digit-Serial Architecture for Montgomery Modular Multiplication
5. An Efficient and Flexible Hardware Implementation of the Dual-Field Elliptic Curve Cryptographic Processor
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