Improving read performance of STT-MRAM based main memories through Smash Read and Flexible Read
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/7422345/7427971/7427985.pdf?arnumber=7427985
Cited by 23 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. CASH: Criticality-Aware Split Hybrid L1 Data Cache;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12
2. WiSE: When Learning Assists Resolving STT-MRAM Efficiency Challenges;IEEE Transactions on Emerging Topics in Computing;2023-01-01
3. Security as an Important Ingredient in Neuromorphic Engineering;2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2022-07
4. Data block manipulation for error rate reduction in STT-MRAM based main memory;The Journal of Supercomputing;2022-03-17
5. CORIDOR: Using CO herence and Tempo R al Local I ty to Mitigate Read D isurbance Err OR in STT-RAM Caches;ACM Transactions on Embedded Computing Systems;2022-01-14
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