Design of a pre-scheduled data bus for advanced encryption standard encrypted system-on-chips-Reference-Cited by-同舟云学术

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Design of a pre-scheduled data bus for advanced encryption standard encrypted system-on-chips

Published:2017-01 Issue: Volume: Page:
ISSN:
Container-title:2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
language:
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Author:

Yang Xiaokun,Wen Wujie

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7847727/7858249/07858373.pdf?arnumber=7858373

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Encryption AXI Transaction Core for Enhanced FPGA Security;Electronics;2022-10-18

2. An Edge Detection IP of Low-Cost System on Chip for Autonomous Vehicles;Transactions on Computational Science and Computational Intelligence;2021

3. An IoT-Edge-Server System with BLE Mesh Network, LBPH, and Deep Metric Learning;Transactions on Computational Science and Computational Intelligence;2021

4. A Lightweight AEAD encryption core to secure IoT applications;2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2020-12-08

5. Towards IP integration on SoC: a case study of high‐throughput and low‐cost wrapper design on a novel IBUS architecture;IET Computers & Digital Techniques;2020-09-18

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