A Look Up Table design with 3D bipolar RRAMs
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/6156603/6164924/06165051.pdf?arnumber=6165051
Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Practical Implementation of Memristor-Based Threshold Logic Gates;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-08
2. Fault tolerant adaptive write schemes for improving endurance and reliability of memristor memories;AEU - International Journal of Electronics and Communications;2018-09
3. Low‐power and area efficient binary coded decimal adder design using a look up table‐based field programmable gate array;IET Circuits, Devices & Systems;2016-05
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5. High-Density and High-Reliability Nonvolatile Field-Programmable Gate Array With Stacked 1D2R RRAM Array;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2016-01
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