A Low-Energy 8-bit CLA Realized by Single-Phase ANT Logic-Reference-Cited by-同舟云学术

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A Low-Energy 8-bit CLA Realized by Single-Phase ANT Logic

Published:2022-09-21 Issue: Volume: Page:
ISSN:
Container-title:2022 International Conference on IC Design and Technology (ICICDT)
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Author:

Kamarajugadda Durga Srikanth¹,Jose Oliver Lexter July A.¹,Yang Lung-Jieh²,Esakki Balasubramanian³,Sampath Sivaperumal⁴,Wang Chua-Chin¹

Affiliation:

1. National Sun Yat-Sen University,Dept. of Electrical Eng.,Kaohsiung,Taiwan,80424

2. Tamkang University,Dept. of Mech. & Electromech. Eng.,Taipei,Taiwan,10650

3. Vel Tech University,Dept. of Mechanical Eng.,Chennai,India,600062

4. Presidency University,Dept. of Electronics & Comm. Eng.,Bengaluru,India,560064

Funder

Ministry of Science and Technology

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9933043/9933065/09933106.pdf?arnumber=9933106

Reference8 articles.

1. A high performance, race eliminated, two phase nonoverlapping clocked All-N-Logic for both strong and subthreshold designs

2. A robust single phase clocking for low power, high-speed VLSI applications

3. Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates

4. A comparison of high-frequency 32-bit dynamic adders with conventional silicon and novel carbon nanotube transistor technologies

5. An Efficient Ultra-Low-Power and Superior Performance Design of Ternary Half Adder Using CNFET and Gate-Overlap TFET Devices

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic;Integration;2024-09

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