Performance Investigation of Graded channel and Dual-Metal Gate-Stack DG MOSFET
Author:
Affiliation:
1. MNNIT Allahabad,Electronics & Communication Engineering,Prayagraj,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10075684/10075722/10075985.pdf?arnumber=10075985
Reference18 articles.
1. Exploring the novel characteristics of fully depleted dual-material gate (DMG) SOI MOSFET using two-dimensional numerical simulation studies
2. Polysilicon gate enhancement of the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFETs with ultrathin gate oxide
3. Improved Switching Speed of a CMOS Inverter Using Work-Function Modulation Engineering
4. Asymmetric Halo CMOSFET to Reduce Static Power Dissipation with Improved Performance
5. Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
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