Testing high-speed SoCs using low-speed ATEs

Author:

Nourani M.,Chin J.

Publisher

IEEE Comput. Soc

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing;Journal of Electronic Testing;2023-02

2. An Ordinal Optimization-Based Approach To Die Distribution Estimation For Massive Multi-site Testing Validation: A Case Study;2021 IEEE European Test Symposium (ETS);2021-05-24

3. Analysis and Evaluation of Multisite Testing for VLSI;IEEE Transactions on Instrumentation and Measurement;2005-10

4. Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction;Journal of Computer Science and Technology;2005-03

5. TAN: a packet switched network for VLSI testing;Proceedings. 12th International Conference on Computer Communications and Networks (IEEE Cat. No.03EX712)

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