Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation-Reference-Cited by-同舟云学术

Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Published:2023-10-28 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)
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Author:

Liu Mingjie¹,Pinckney Nathaniel¹,Khailany Brucek¹,Ren Haoxing¹

Affiliation:

1. NVIDIA Corporation

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10323590/10323543/10323812.pdf?arnumber=10323812

Reference34 articles.

1. RTLLM: An open-source benchmark for design rtl generation with large language model;lu;ArXiv Preprint,2023

2. Benchmarking large language models for auto-mated verilog rtl code generation;thakur;2023 Design Automation & Test in Europe Conference & Exhibition (DATE),2023

3. Training language models to follow instructions with human feedback;ouyang;Advances in neural information processing systems,2022

4. Finetuned language models are zero-shot learners;wei;ArXiv Preprint,2021

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