Design of CMOS Device Process Sensor in 28 nm FD-SOI with 2 % of Frequency Spread
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9665417/9665446/09665465.pdf?arnumber=9665465
Reference28 articles.
1. Compensation of systematic variations through optimal biasing of SRAM wordlines
2. A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation
3. Lack of Spatial Correlation in MOSFET Threshold Voltage Variation and Implications for Voltage Scaling
4. On-chip process variation-tracking through an all-digital monitoring architecture
5. Variation-Sensitive Monitor Circuits for Estimation of Global Process Parameter Variation
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