VECBEE: A Versatile Efficiency–Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis-Reference-Cited by-同舟云学术

VECBEE: A Versatile Efficiency–Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis

Published:2022-11 Issue:11 Volume:41 Page:5085-5099
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Su Sanbao¹,Meng Chang¹^ORCID,Yang Fan²^ORCID,Shen Xiaolong³,Ni Leibin³,Wu Wei³,Wu Zhihang³,Zhao Junfeng³,Qian Weikang⁴^ORCID

Affiliation:

1. University of Michigan–Shanghai Jiao Tong University Joint Institute, Shanghai Jiao Tong University, Shanghai, China

2. School of Microelectronics and the State Key Laboratory of ASIC and System, Fudan University, Shanghai, China

3. Central Research Institute, 2012 Laboratories, Huawei Technologies Company Ltd., Shenzhen, China

4. University of Michigan–Shanghai Jiao Tong University Joint Institute and the MoE Key Laboratory of Artificial Intelligence, Shanghai Jiao Tong University, Shanghai, China

Funder

National Key Research and Development Program of China

State Key Laboratory of ASIC and System Open Research

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx7/43/9928799/09706238.pdf?arnumber=9706238

Reference55 articles.

1. A methodology for energy-quality tradeoff using imprecise hardware

2. An Analytical Approach for Error PMF Characterization in Approximate Circuits

3. DALS

4. Evolutionary Approach to Approximate Digital Circuits Design

5. Statistically certified approximate logic synthesis

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1. Data-Driven Feature Selection Framework for Approximate Circuit Design;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11

2. HEDALS: Highly Efficient Delay-Driven Approximate Logic Synthesis;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11

3. DASALS: Differentiable Architecture Search-Driven Approximate Logic Synthesis;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

4. AccALS: Accelerating Approximate Logic Synthesis by Selection of Multiple Local Approximate Changes;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09