A High-Throughput Full-Dataflow MobileNetv2 Accelerator on Edge FPGA

Author:

Jiang Weixiong1ORCID,Yu Heng2ORCID,Ha Yajun3ORCID

Affiliation:

1. School of Information Science and Technology, ShanghaiTech University, Shanghai, China

2. School of Computer Science, University of Nottingham Ningbo China, Ningbo, China

3. School of Information Science and Technology and the Shanghai Engineering Research Center of Energy Efficient and Custom AI IC, ShanghaiTech University, Shanghai, China

Funder

Natural Science Foundation of China

Shanghai Science and Technology Commission Funding

National Natural Science Foundation of China

Ningbo Science and Technology Bureau

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Reference39 articles.

1. Deep Residual Learning for Image Recognition

2. Same, same but different: Recovering neural network quantization error through weight factorization;meller;Proc Int Conf Mach Learn (ICML),2019

3. Optimizing CNN-based Segmentation with Deeply Customized Convolutional and Deconvolutional Architectures on FPGA

4. Compensated-DNN

5. Squeeze-and-Excitation Networks

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