A Low-Latency FPGA Accelerator for YOLOv3-Tiny With Flexible Layerwise Mapping and Dataflow-Reference-Cited by-同舟云学术

A Low-Latency FPGA Accelerator for YOLOv3-Tiny With Flexible Layerwise Mapping and Dataflow

Published:2023 Issue: Volume: Page:1-14
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Kim Minsik¹^ORCID,Oh Kyoungseok²,Cho Youngmock²^ORCID,Seo Hojin²^ORCID,Nguyen Xuan Truong³^ORCID,Lee Hyuk-Jae⁴^ORCID

Affiliation:

1. Department of Electrical Engineering and Computer Sciences, Univeristy of Michigan, Ann Arbor, MI, USA

2. Department of Electrical and Computer Engineering, College of Engineering, Seoul National University, Seoul, South Korea

3. Department of Next-generation Semiconductor Convergence and Open Sharing System (COSS), Seoul National University, Seoul, South Korea

4. Inter-University Semiconductor Research Center (ISRC) and the Department of Electrical and Computer Engineering, College of Engineering, Seoul National University, Seoul, South Korea

Funder

Ministry of Trade, Industry and Energy

Korea Government

AI accelerator-optimized neural network automatic generation technology and open service platform development)

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/4358591/10360333.pdf?arnumber=10360333

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