A Don’t-Care-Based Approach to Reducing the Multiplicative Complexity in Logic Networks-Reference-Cited by-同舟云学术

A Don’t-Care-Based Approach to Reducing the Multiplicative Complexity in Logic Networks

Published:2022-11 Issue:11 Volume:41 Page:4821-4825
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Liu Hsiao-Lun¹^ORCID,Li Yi-Ting¹,Chen Yung-Chih²,Wang Chun-Yao¹

Affiliation:

1. Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan

2. Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan

Funder

Ministry of Science and Technology of Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

Reference20 articles.

1. A power optimization toolbox for logic synthesis and mapping;jang;Proc IWLS,2009

2. Improved garbled circuit: Free XOR gates and applications;kolesnikov;Proc ICALP,2008

3. SAT-based complete don’t-care computation for network optimization;mishchenko;Proc DATE,2005

4. An algorithm for linear, affine and spectral classification of Boolean functions;miller;Proc Int Workshop Boolean Problems,2018

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3. Striving for Both Quality and Speed: Logic Synthesis for Practical Garbled Circuits;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

4. Generating Lower-Cost Garbled Circuits: Logic Synthesis Can Help;2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST);2023-05-01