Generating Lower-Cost Garbled Circuits: Logic Synthesis Can Help
Author:
Affiliation:
1. EPFL Lausanne,Integrated Systems Laboratory,Switzerland
Funder
Synopsys
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10132842/10132914/10133215.pdf?arnumber=10133215
Reference29 articles.
1. Garbling Gadgets for Boolean and Arithmetic Circuits
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3. The multiplicative com-plexity of 6-variable boolean functions;ç alik;Cryptography and Communi-cations,2019
4. On the multiplicative complexity of Boolean functions over the basis (∧,⊕,1)
5. A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks
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2. Striving for Both Quality and Speed: Logic Synthesis for Practical Garbled Circuits;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28
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