A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks-Reference-Cited by-同舟云学术

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A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks

Published:2020-03 Issue: Volume: Page:
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Container-title:2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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Author:

Testa Eleonora,Soeken Mathias,Riener Heinz,Amaru Luca,Micheli Giovanni De

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9112295/9116186/09116467.pdf?arnumber=9116467

Cited by 20 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Multiplication Complexity Optimization based on Quantified Boolean Formulas;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

2. Toffoli-depth reduction method preserving in-place quantum circuits and its application to SHA3-256;Quantum Information Processing;2024-04-18

3. Garbled Circuits Reimagined: Logic Synthesis Unleashes Efficient Secure Computation;Cryptography;2023-11-23

4. A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11

5. Striving for Both Quality and Speed: Logic Synthesis for Practical Garbled Circuits;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

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