Partial Sum Quantization for Reducing ADC Size in ReRAM-Based Neural Network Accelerators-Reference-Cited by-同舟云学术

Partial Sum Quantization for Reducing ADC Size in ReRAM-Based Neural Network Accelerators

Published:2023-12 Issue:12 Volume:42 Page:4897-4908
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Azamat Azat¹^ORCID,Asim Faaiz²,Kim Jintae³^ORCID,Lee Jongeun²^ORCID

Affiliation:

1. Department of Computer Science and Engineering, Ulsan National Institute of Science and Technology, Ulsan, South Korea

2. Department of Electrical Engineering, Ulsan National Institute of Science and Technology, Ulsan, South Korea

3. Department of Electrical and Electronics Engineering, Konkuk University, Seoul, South Korea

Funder

IITP Grant through ITRC Support Program

IITP Grant through Artificial Intelligence Graduate School Program

NRF Grant through National R&D Program

MSIT of Korea

Free Innovative Research Fund of UNIST

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

Reference34 articles.

1. PACT: Parameterized clipping activation for quantized neural networks;choi;arXiv 1805 06085,2018

2. Learning to quantize deep networks by optimizing quantization intervals with task loss;jung;arXiv 1808 05779,2018

4. Training and inference with integers in deep neural networks;wu;arXiv 1802 04680,2018

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