Preplacement Net Length and Timing Estimation by Customized Graph Neural Network-Reference-Cited by-同舟云学术

Preplacement Net Length and Timing Estimation by Customized Graph Neural Network

Published:2022-11 Issue:11 Volume:41 Page:4667-4680
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Xie Zhiyao¹^ORCID,Liang Rongjian²^ORCID,Xu Xiaoqing³,Hu Jiang⁴,Chang Chen-Chia⁵,Pan Jingyu⁵^ORCID,Chen Yiran⁵^ORCID

Affiliation:

1. Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong, SAR

2. ASIC and VLSI Research Group, Nvidia, Austin, TX, USA

3. Arm Research, Austin, TX, USA

4. Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA

5. Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA

Funder

National Science Foundation

Semiconductor Research Corporation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

Reference44 articles.

1. Anubis: A new benchmark for incremental synthesis;possignolo;Proc Int Workshop Logic Synth,2017

5. A deep learning methodology to proliferate golden signoff timing;han;Proc DATE,2014

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4. Aging -aware Path Timing Prediction via Graph Representation Learning;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

5. Integration of Shift-Left Updates into Logic Synthesis and Macro Placement;2024 Conference of Science and Technology for Integrated Circuits (CSTIC);2024-03-17