Test Chips With Scan-Based Logic Arrays

Author:

Chen Yu-HsiangORCID,Hsu Chia-MingORCID,Lee Kuen-JongORCID

Funder

Ministry of Science and Technology of Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Diagnostic Test Point Insertion and Test Compaction;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-02

2. Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks;2022 IEEE International Test Conference (ITC);2022-09

3. Diagnosing Transition Delay Faults under Scan-Based Logic Array;2022 IEEE International Test Conference in Asia (ITC-Asia);2022-08

4. Reconfigurable Scan Architecture for High Diagnostic Resolution;IEEE Access;2021

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