Enhancement of Sram Read and Write Noise Margin by Device Performance Adjustment
Author:
Affiliation:
1. Semiconductor Manufacturing North China (Beijing) Corporation (SMNC),Beijing,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10531806/10531771/10531959.pdf?arnumber=10531959
Reference10 articles.
1. A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications;Koichi;IEEE journal of solid-state circuits,2005
2. Static noise margin analysis of SRAM cell for high speed application;Debasis;International Journal of Computer Science Issues (IJCSI),2010
3. Impact of threshold voltage fluctuation due to random telegraph noise on scaled-down SRAM
4. Application of Extreme Value Theory to Statistical Analyses of Worst Case SRAM Data Retention Voltage
5. Nanometer Variation-Tolerant SRAM
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