A 5.3-GHz programmable divider for HiPerLAN in 0.25-/spl mu/m CMOS-Reference-Cited by-同舟云学术

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A 5.3-GHz programmable divider for HiPerLAN in 0.25-/spl mu/m CMOS

Published:2000-07 Issue:7 Volume:35 Page:1019-1024
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Krishnapura N.,Kinget P.R.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/18446/00848211.pdf?arnumber=848211

Cited by 45 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Spur reduction architecture for multiphase fractional PLLs;IET Circuits, Devices & Systems;2019-11

3. A 0.5 V, 9-GHz Sub-Integer Frequency Synthesizer Using Multi-Phase Injection-Locked Prescaler for Phase-Switching-Based Programmable Division With Automatic Injection-Lock Calibration in 45-nm CMOS;IEEE Transactions on Circuits and Systems II: Express Briefs;2019-05

4. Design and optimization of the ring oscillator based injection locked frequency dividers;Microelectronics Journal;2018-02

5. A novel pulse swallow based frequency divider circuit for a phase-locked loops;Analog Integrated Circuits and Signal Processing;2017-04-22

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