A novel pulse swallow based frequency divider circuit for a phase-locked loops
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/article/10.1007/s10470-017-0979-2/fulltext.html
Reference49 articles.
1. Hati, M. K., & Bhattacharyya, T. K. (2015). A PFD and charge pump switching circuit to optimize the output phase noise of the PLL in 0.13- $$\upmu$$ μ m CMOS. In 2015 International conference on VLSI systems, architecture, technology and applications (pp. 1–6)
2. Hati, M. K., & Bhattacharyya, T. K. (2013). A high output resistance, wide swing and perfect current matching charge pump having switching circuit for PLL. Microelectronics Journal, 44(8), 649–657.
3. Hati, M. K., & Bhattacharyya, T. K. (2015). Efficient design technique for pulse swallow based fractional-N frequency divider. In International symposium on circuits and systems (pp 457–460).
4. Hati, M. K., & Bhattacharyya, T. K. (2016). A fast automatic frequency and amplitude control LC-VCO circuit with noise filtering technique for a fractional-N PLL frequency synthesizer. Microelectronics Journal, 52(2), 134–146.
5. Shin, J., & Shin, H. (2012). A 1.9–3.8 GHz $$\Delta \Sigma$$ Δ Σ fractional-N PLL frequency synthesizer with fast auto-calibration of loop bandwidth and VCO frequency. IEEE Journal of Solid-State Circuits, 47(3), 665–667.
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