A 1.5fJ/conv-step 10b 100kS/s SAR ADC with gain-boosted dynamic comparator-Reference-Cited by-同舟云学术

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A 1.5fJ/conv-step 10b 100kS/s SAR ADC with gain-boosted dynamic comparator

Published:2017-11 Issue: Volume: Page:
ISSN:
Container-title:2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)
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Author:

Tang Xiyuan,Chen Long,Song Jeonggoo,Sun Nan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8226344/8240197/08240258.pdf?arnumber=8240258

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier;IEEE Journal of Solid-State Circuits;2023-09

2. Performance analysis of high-speed, low-power comparators;Highlights in Science, Engineering and Technology;2022-12-27

3. Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-06

4. Towards Effective Music Therapy for Mental Health Care Using Machine Learning Tools: Human Affective Reasoning and Music Genres;Journal of Artificial Intelligence and Soft Computing Research;2020-12-03

5. A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier;IEEE Journal of Solid-State Circuits;2020-12

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