A smart-offset analog LDO with 0.3V minimum input voltage and 99.1% current efficiency
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/8226344/8240197/08240268.pdf?arnumber=8240268
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 0.5–1-V Time–Voltage Hybrid Domain Dual-Loop Analog LDO With Wide-Bandwidth High PSR in 28 nm;IEEE Journal of Solid-State Circuits;2024
2. A 0.3V-VIN, 0.015ps-FoM Fully Integrated Analog-Assisted Digital LDO With Dual-Negative Gate Control and Adaptive Transient Recovery Path;IEEE Transactions on Power Electronics;2023-01
3. A 0.5–1 V, −68 dB Power Supply Rejection Capacitorless Analog LDO Using Voltage-to-Time Conversion in 28-nm CMOS;IEEE Journal of Solid-State Circuits;2022-08
4. A 0.009mm2, 0-230mA Wide-range Load Current Output Capacitor-less Low Dropout Regulator for High Bandwidth Memory parallel IOs;2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID);2022-02
5. A Class-D FVF LDO With Multi-Level PWM Gate Control, 280-ns Settling Time, and No Overshoot/Undershoot;IEEE Transactions on Circuits and Systems I: Regular Papers;2020-12
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