TLM-NoC: Two Level Mesh Network-on-Chip for Performance Improvement
Author:
Affiliation:
1. National Institute of Technology Karnataka,Department of Computer Science and Engineering,Mangalore,Bharat,575025
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9780876/9780861/09781058.pdf?arnumber=9781058
Reference13 articles.
1. A shortly connected mesh topology for high performance and energy efficient network-on-chip architectures
2. Smart-Hop Arbitration Request Propagation
3. Smart++ reducing cost and improving efficiency of multi-hop bypass in noc routers;pérez;Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip,0
4. Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures
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1. Optimizing Network-on-Chip using metaheuristic algorithms: A comprehensive survey;Microprocessors and Microsystems;2023-11
2. Design of a Fault-Tolerant Pseudo-3D Routing;2023 IEEE International Test Conference India (ITC India);2023-07-23
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