Analysis of the Security Vulnerabilities of 2.5-D and 3-D Integrated Circuits-Reference-Cited by-同舟云学术

Analysis of the Security Vulnerabilities of 2.5-D and 3-D Integrated Circuits

Published:2022-04-06 Issue: Volume: Page:
ISSN:
Container-title:2022 23rd International Symposium on Quality Electronic Design (ISQED)
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Author:

Rao Vaibhav Venugopal¹,Sasan Avesta²,Savidis Ioannis¹

Affiliation:

1. Drexel University,Philadelphia,Pennslyvania,19104

2. University of California, Davis,Davis,California,95616

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9806045/9806137/09806155.pdf?arnumber=9806155

Reference30 articles.

1. Transistor-level camouflaged logic locking method for monolithic 3D IC security

2. Full Chip Thermal Analysis of Planar (2-D) and Vertically Integrated (3-D) High Performance ICs;im;Proceedings of the IEEE International Electron Devices Meeting,2000

3. A Survey of Hardware Trojan Taxonomy and Detection

4. Exploiting Proximity Information in a Satisfiability Based Attack Against Split Manufactured Circuits

5. Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs

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1. Harnessing Heterogeneity for Targeted Attacks on 3-D ICs;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12

2. DHRCA: A Design of Security Architecture Based on Dynamic Heterogeneous Redundant for System on Wafer;IET Information Security;2024-04-12

3. On Hardware Security and Trust for Chiplet-Based 2.5D and 3D ICs: Challenges and Innovations;IEEE Access;2024

4. Reduction of Toggling Activity Using Novel LFSR Driven Logic for ULSI Circuits;2023 International Conference on Next Generation Electronics (NEleX);2023-12-14