Reduction of Toggling Activity Using Novel LFSR Driven Logic for ULSI Circuits
Author:
Affiliation:
1. Amrita school of Engineering, Amrita Vishwa Vidyapeetam,Department of Electronics and Communication Engineering,Bengaluru,India
2. Tessolve Semiconductors Limited,Bengaluru,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10420829/10420849/10421291.pdf?arnumber=10421291
Reference22 articles.
1. Power Optimization of VLSI Scan under Test using X-Filling Technique
2. Early Register Transfer Level (RTL) power estimation in real-time System-on-Chips (SoCs);Priya;E.L.Journal of Integrated Science and Technology,2023
3. Application Specific Testing for VLSI Benchmark Circuits
4. A compaction based MT filling technique for low-power test set generation
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