Timing-constrained yield-driven redundant via insertion-Reference-Cited by-同舟云学术

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Timing-constrained yield-driven redundant via insertion

Published:2008-11 Issue: Volume: Page:
ISSN:
Container-title:APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
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Author:

Jin-Tai Yan ,Zhi-Wei Chen ,Bo-Yi Chiang ,Yu-Min Lee

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4723905/4745943/04746363.pdf?arnumber=4746363

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Redundant Via Insertion for MP-DSAL;Physical Design and Mask Synthesis for Directed Self-Assembly Lithography;2018

2. Redundant Via Insertion for DSAL;Physical Design and Mask Synthesis for Directed Self-Assembly Lithography;2018

3. Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits;Microelectronics Journal;2012-02

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