A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics-Reference-Cited by-同舟云学术

A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics

Published:2021-09-13 Issue: Volume: Page:
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Container-title:ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)
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Author:

Yoon Hojun,Jung Wonjoo,Park Jaewoo,Byun Jindo,Jin Hyungmin,Cho Hyunyoon,Kim Youngmin,Lim Baekjin,Cho Young-Chul,Choi Youngdon,Choi Jung-Hwan,Ko Hyungjong,Yoo Changsik,Lee Sang-Hyun

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9567713/9567736/09567848.pdf?arnumber=9567848

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 0.001-mm², 1.15–11-GHz Background Quadrature Phase and Duty-Cycle Error Corrector Using a NAND- Based Phase Detector in 28-nm CMOS;IEEE Solid-State Circuits Letters;2024

2. An 8-GHz Octa-Phase Clock Corrector with Phase and Duty-Cycle Correction in 40-nm CMOS;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06

3. A 30 kHz - 3 GHz Clock Duty-Cycle Corrector Circuit for CMOS Integrated Digital Electronic Systems;2023 30th International Conference on Mixed Design of Integrated Circuits and System (MIXDES);2023-06-29

4. A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range;Electronics;2023-06-16

5. 28.5 A 900µW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25^%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces;2023 IEEE International Solid- State Circuits Conference (ISSCC);2023-02-19