A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm

Author:

Sridharan Amitesh1,Angizi Shaahin2,Cherupally Sai Kiran1,Zhang Fan1,Seo Jae-Sun1,Fan Deliang1

Affiliation:

1. Arizona State University,USA

2. New Jersey Institute of Technology,USA

Funder

NSF

SRC

DARPA

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. On-Device Continual Learning With STT-Assisted-SOT MRAM-Based In-Memory Computing;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-08

2. A 106TOPS/W SRAM Compute-in-Memory Macro in 28NM With Reconfigurable Bitwise Operation for AI;2024 Conference of Science and Technology for Integrated Circuits (CSTIC);2024-03-17

3. A 65nm RRAM Compute-in-Memory Macro for Genome Sequencing Alignment;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11

4. Comparative Study of Low Bit-width DNN Accelerators: Opportunities and Challenges;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06

5. DSPIMM: A Fully Digital SParse In-Memory Matrix Vector Multiplier for Communication Applications;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09

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