A 106TOPS/W SRAM Compute-in-Memory Macro in 28NM With Reconfigurable Bitwise Operation for AI
Author:
Affiliation:
1. Institute of VLSI Design, School of Micro-Nano Electronics, Zhejiang University,Hangzhou,China,311200
2. Zhejiang Lab,Hangzhou,China,311121
3. College of computer science and technology, Zhejiang University
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10531806/10531771/10531930.pdf?arnumber=10531930
Reference3 articles.
1. An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications;Chih
2. A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm
3. A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications
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