A Low-Power and Energy-Efficient D-Band CMOS Four-Channel Receiver with Integrated LO Generation for Digital Beamforming Arrays
Author:
Affiliation:
1. Berkeley Wireless Research Center (BWRC), University of California,Berkeley,CA
Funder
Semiconductor Research Corporation
DARPA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9911257/9911222/09911448.pdf?arnumber=9911448
Reference7 articles.
1. A 122-168GHz Radar/Communication Fusion-Mode Transceiver with 30GHz Chirp Bandwidth, 13dBm Psat, and 8.3dBm OP1dB in 28nm CMOS
2. A Fully Integrated, Dual Channel, Flip Chip Packaged 113 GHz Transceiver in 28nm CMOS supporting an 80 Gb/s Wireless Link
3. A 71-to-86-GHz 16-Element by 16-Beam Multi-User Beamforming Integrated Receiver Sub-Array for Massive MIMO
4. A 57–74-GHz Tail-Switching Injection-Locked Frequency Tripler in 28-nm CMOS
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