A 128-Gb/s <i>D</i>-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET-Reference-Cited by-同舟云学术

A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET

Published:2023-12 Issue:12 Volume:58 Page:3364-3379
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Agrawal Abhishek¹^ORCID,Whitcombe Amy²^ORCID,Shin Woorim¹,Bhat Ritesh¹^ORCID,Kundu Somnath¹^ORCID,Sagazio Peter¹^ORCID,Chandrakumar Hariprasad³^ORCID,Brown Thomas W.³^ORCID,Carlton Brent R.¹^ORCID,Hull Christopher¹,Callender Steven¹^ORCID,Pellerano Stefano¹

Affiliation:

1. Intel Corporation, Hillsboro, OR, USA

2. Intel Corporation, Santa Clara, CA, USA

3. Advanced Design Group in Technology Development Organization, Intel Corporation, Hillsboro, OR, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10328904/10273376.pdf?arnumber=10273376

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4. A 10-GS/s 8-bit 2850-μm² Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC

5. Fully Integrated 2D Scalable TX/RX Chipset for D-Band Phased-Array-on-Glass Modules

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