A Pipeline ADC with Negative C-assisted SC Amplifier Canceling Gain Error and Nonlinearity
Author:
Affiliation:
1. School of Electrical Engineering, KAIST,Daejeon,Korea
2. Samsung Electronics Co., Ltd.,Hwaseong,Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9911257/9911222/09911468.pdf?arnumber=9911468
Reference10 articles.
1. A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion
2. A Pipeline SAR ADC With Second-Order Interstage Gain Error Shaping
3. A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS
4. A 14b 60 MS/s Pipelined ADC Adaptively Cancelling Opamp Gain and Nonlinearity
5. A single-channel, 600Msps, 12bit, ringamp-based pipelined ADC in 28nm CMOS
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. An 11bit 360MS/s Pipelined SAR ADC with Dynamic Negative-C Assisted Residue Amplifier;2023 IEEE Asian Solid-State Circuits Conference (A-SSCC);2023-11-05
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