A 13-bit 70MS/s SAR-Assisted 2-bit/cycle Cyclic ADC with Offset Cancellation and Slack-Borrowing Logic
Author:
Affiliation:
1. National University of Singapore,Department of Electrical and Computer Engineering,Singapore
2. Digipen Institute of Technology,Singapore
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10268677/10268683/10268690.pdf?arnumber=10268690
Reference8 articles.
1. A 0.4-to-40MS/s 75.7dB-SNDR fully dynamic eventdriven pipelined ADC with 3-stage cascoded floating inverter amplifier;tang;IEEE Dig Tech Papers Int Solid-State Circ Conf (ISSCC),2021
2. A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier
3. A 0.02-mm$^{2}$ 9-Bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS Technology
4. A 14b extended counting ADC implemented in a 24Mpixel APS-C CMOS image sensor
5. A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration;zhou;Proc IEEE Symp VLSI Circuits,2014
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