A 0-to-35mA NMOS Capacitor-Less LDO with Dual-Loop Regulation Achieving 3ns Response Time and 1pF-to-10nF Loading Range-Reference-Cited by-同舟云学术

A 0-to-35mA NMOS Capacitor-Less LDO with Dual-Loop Regulation Achieving 3ns Response Time and 1pF-to-10nF Loading Range

Published:2023-09-11 Issue: Volume: Page:
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Container-title:ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)
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Author:

Hsu Wen-Yang¹,Aymerich Joan¹,Yang Xiaolin¹,Sawigun Chutham¹,Coppejans Philippe¹,Lopez Carolina Mora¹

Affiliation:

1. imec,Leuven,Belgium

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10268677/10268683/10268699.pdf?arnumber=10268699

Reference11 articles.

1. A 130nm hybrid low doprout regulator based on switched mode control for digital load circuits;nasir;ESSCIRC,2016

2. A 65nm Edge-Chasing Quantizer-Based Digital LDO Featuring 4.58 ps-FoM and Side-Channel-Attack Resistance;he,2020

3. A fast-transient and widerange output capacitor-less NMOS LDO regulator with adaptive-gain nested miller compensation and pre-emphasis inverse biasing;park;IEEE A-SSCC Taipei,2022

4. A 310-nA Quiescent Current 3-fs-FoM Fully Integrated Capacitorless Time-Domain LDO With Event-Driven Charge Pump and Feedforward Transient Enhancement

5. A Dynamically High-Impedance Charge-Pump-Based LDO With Digital-LDO-Like Properties Achieving a Sub-4-fs FoM

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