FPGA-based SHA-3 acceleration on a 32-bit processor via instruction set extension-Reference-Cited by-同舟云学术

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FPGA-based SHA-3 acceleration on a 32-bit processor via instruction set extension

Published:2015-06 Issue: Volume: Page:
ISSN:
Container-title:2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)
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Author:

Wang Yi,Shi Youhua,Wang Chao,Ha Yajun

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7270873/7285012/07285111.pdf?arnumber=7285111

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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