Maximizing the Potential of Custom RISC-V Vector Extensions for Speeding up SHA-3 Hash Functions
Author:
Affiliation:
1. Delft University of Technology,The Netherlands
2. Leiden University,The Netherlands
3. Radboud University,The Netherlands
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10136870/10136706/10137009.pdf?arnumber=10137009
Reference15 articles.
1. FPGA-based SHA-3 acceleration on a 32-bit processor via instruction set extension
2. Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor
3. Vector Instruction Set Extensions for Efficient Computation of Keccak
4. Hardware implementation of a SHA-3 application-specific instruction set processor
5. A synthesis method-ology for hybrid custom instruction and coprocessor generation for extensible processors;sun;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2007
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