An 8.5–12.5GHz multi-PLL clock architecture with LC PLL and Ring PLL for multi-lane multi-protocol SerDes

Author:

He Yajun,Wang Ziqiang,Liu Han,Lv Fangxu,Yuan Shuai,Zhang Chun,Xie Xiang,Jiang Hanjun

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

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