Fully Integrated Phase-Locked Loop with Lower Power Consumption Current Controlled Oscillator
Author:
Affiliation:
1. Chung Yuan Christian University,Dep. of Electronic Engineering,Taoyuan,Taiwan, R.O.C.
2. National Taiwan University of Science and Technology,Dep. of Electronic Engineering,Taipei,Taiwan, R.O.C.
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10649022/10649036/10649384.pdf?arnumber=10649384
Reference4 articles.
1. A 5.5-GHz 16-mW fast-locking frequency synthesizer in 0.18-μm CMOS
2. An 8.5–12.5GHz multi-PLL clock architecture with LC PLL and Ring PLL for multi-lane multi-protocol SerDes
3. A low-supply PLL with Enhanced Cascode Compensation and a low-supply-sensitivity CCO
4. A 1.2GHz adaptive bandwidth type-I PLL using a digital lock detector
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