Research Challenges for On-Chip Interconnection Networks-Reference-Cited by-同舟云学术

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Research Challenges for On-Chip Interconnection Networks

Published:2007-09 Issue:5 Volume:27 Page:96-108
ISSN:0272-1732
Container-title:IEEE Micro
language:
Short-container-title:IEEE Micro

Author:

Owens J.D.,Dally W.J.,Ho R.,Jayasimha D.N.,Keckler S.W.,Li-Shiuan Peh

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/40/4378774/04378787.pdf?arnumber=4378787

Cited by 232 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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4. Electronic Computer-Aided Design for Low-Level Modeling of Networks-on-Chip;IEEE Access;2024

5. Electronics Hardware Chip Design for Router–Router Communication;Proceedings of the National Academy of Sciences, India Section A: Physical Sciences;2023-09-30

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