Electronic Computer-Aided Design for Low-Level Modeling of Networks-on-Chip-Reference-Cited by-同舟云学术

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Electronic Computer-Aided Design for Low-Level Modeling of Networks-on-Chip

Published:2024 Issue: Volume:12 Page:48750-48763
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Lezhnev Evgeny V.¹^ORCID,Zunin Vladimir V.¹^ORCID,Amerikanov Aleksandr A.¹^ORCID,Romanov Aleksandr Y.¹^ORCID

Affiliation:

1. HSE University, Moscow, Russia

Funder

Basic Research Program at the National Research University Higher School of Economics

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/6287639/10380310/10483007.pdf?arnumber=10483007

Reference53 articles.

1. Next generation on-chip networks

2. Resource-awareness on heterogeneous MPSoCs for image processing

3. Design and Applications for Embedded Networks-on-Chip on FPGAs

4. The Chip Is the Network: Toward a Science of Network-on-Chip Design

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Cycle-accurate multi-FPGA platform for accelerated emulation of large on-chip networks;The Journal of Supercomputing;2024-06-23

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