CIFER: A 12nm, 16mm<sup>2</sup>, 22-Core SoC with a 1541 LUT6/mm<sup>2</sup> 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA-Reference-Cited by-同舟云学术

CIFER: A 12nm, 16mm², 22-Core SoC with a 1541 LUT6/mm² 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA

Published:2023-04 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE Custom Integrated Circuits Conference (CICC)
language:
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Author:

Chang Ting-Jung¹,Li Ang¹,Gao Fei¹,Ta Tuan²,Tziantzioulis Georgios¹,Ou Yanghui²,Wang Moyang²,Tu Jinzheng¹,Xu Kaifeng¹,Jackson Paul J.¹,Ning August¹,Chirkov Grigory¹,Orenes-Vera Marcelo¹,Agwa Shady²,Yan Xiaoyu²,Tang Eric²,Balkind Jonathan³,Batten Christopher²,Wentzlaff David¹

Affiliation:

1. Princeton University,Santa Barbara

2. 2Cornell University,Santa Barbara

3. University of California,Santa Barbara

Funder

Advanced Research Projects Agency

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10121189/10121178/10121294.pdf?arnumber=10121294

Reference6 articles.

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Dynamic Resource Management in Reconfigurable SoC for Multi-Tenancy Support;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. MuchiSim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems;2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS);2024-05-05

3. SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks;2024 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS);2024-04-17

4. CIFER: A Cache-Coherent 12-nm 16-mm² SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm² Synthesizable eFPGA;IEEE Solid-State Circuits Letters;2023