CIFER: A Cache-Coherent 12-nm 16-mm2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable eFPGA

Author:

Li Ang1ORCID,Chang Ting-Jung2,Gao Fei1ORCID,Ta Tuan3ORCID,Tziantzioulis Georgios1,Ou Yanghui3ORCID,Wang Moyang3,Tu Jinzheng1ORCID,Xu Kaifeng1ORCID,Jackson Paul1ORCID,Ning August1,Chirkov Grigory1ORCID,Orenes-Vera Marcelo2,Agwa Shady3ORCID,Yan Xiaoyu3,Tang Eric3,Balkind Jonathan4ORCID,Batten Christopher3ORCID,Wentzlaff David1

Affiliation:

1. Department of Electrical and Computer Engineering, Princeton University, Princeton, NJ, USA

2. Department of Computer Science, Princeton University, Princeton, NJ, USA

3. Department of Electrical and Computer Engineering, Cornell University, Ithaca, NY, USA

4. Department of Computer Science, University of California at Santa Barbara, Santa Barbara, CA, USA

Funder

Air Force Research Laboratory

Defense Advanced Research Projects Agency

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Reference16 articles.

1. A Fully Programmable eFPGA-Augmented SoC for Smart Power Applications

2. Efficiently Supporting Dynamic Task Parallelism on Heterogeneous Cache-Coherent Systems

3. Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes

4. 12.1 an FPGA-accelerated fully nonvolatile microcontroller unit for sensor-node applications in 40nm CMOS/MTJ-hybrid technology achieving 47.14 ?W operation at 200MHz;natsui;Proc ISSCC,0

5. Duet: Creating Harmony between Processors and Embedded FPGAs

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