Weightings in Incremental ADCs: A Tutorial Review
Author:
Affiliation:
1. University of Macau
2. Shanghai Jiao Tong University
Funder
Technology Development
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10121189/10121178/10121252.pdf?arnumber=10121252
Reference43 articles.
1. A 0.014mm2 10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRR
2. A 1.25 MS/S Two-Step Incremental ADC with 100DB DR and 110DB SFDR;katayama;IEEE Symposium on VLSI Circuits,2018
3. A4.96 ?W15b Self-Timed Dynamic-AmplifierBased Incremental Zoom ADC;liu;International Solid-State Circuits Conference (ISSCC),2022
4. A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS
5. A 16-bit 1KHz bandwidth micro-power multi-step incremental ADC for multi-channel sensor interface
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